Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

摘要

Off-chip buses account for a significant portion of the total system powerconsumed in embedded systems. Bus encoding schemes have been proposed tominimize power dissipation, but none has been demonstrated to be optimal withrespect to any measure. In this paper, we give the first provably optimal andexplicit (polynomial-time constructible) families of memoryless codes forminimizing bit transitions in off-chip buses. Our results imply that havingaccess to a clock does not make a memoryless encoding scheme that minimizes bittransitions more powerful.